Feed-forward technique for power supply rejection ratio improvement of bit line

ABSTRACT

An image sensor read out circuit includes a first current mirror circuit in which a second current conducted through a second current path is controlled in response to a first current conducted through the first current path. The second current is conducted through an amplifier transistor of a pixel circuit. A first current source is coupled to the first current path to provide a substantially constant current component of the first current. A second current source is coupled to a power supply rail of the pixel circuit and coupled to the first current path to provide a ripple current component of the first current. The ripple current component provided by the second current source is responsive to a ripple in the power supply rail. The first current is responsive to a sum of the currents from the first and second current sources.

BACKGROUND INFORMATION

1. Field of the Disclosure

The present invention relates generally to image sensors. Morespecifically, examples of the present invention are related to circuitsthat read out image data from image sensor pixel cells.

2. Background

Image sensors have become ubiquitous. They are widely used in digitalcameras, cellular phones, security cameras, as well as, medical,automobile, and other applications. The technology used to manufactureimage sensors, and in particular, complementarymetal-oxide-semiconductor (CMOS) image sensors, has continued to advanceat great pace. For example, the demands of higher resolution and lowerpower consumption have encouraged the further miniaturization andintegration of CMOS image sensors.

In a conventional CMOS active pixel sensor, image charge is transferredfrom a photosensitive device (e.g., a photo diode) and is converted to avoltage signal inside the pixel cell on a floating diffusion node. Inconventional CMOS image sensors, an amplifier such as a source followercircuit is used in the pixel cells to amplify the signal on the floatingdiffusion node to output the image data to the bit lines, which are readby the column read out circuitry. Limited by the design and layoutconstraints of pixel cells, the source follower circuits can suffer froman unsatisfactory power supply rejection ratio, such as −20 dB. Anunsatisfactory power supply rejection ratio can present many challenges,including noise from power supplies that can enter into the outputsignal path. Furthermore, the ripple of power supplies can causeunwanted horizontal ripple in the captured image.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention aredescribed with reference to the following figures, wherein likereference numerals refer to like parts throughout the various viewsunless otherwise specified.

FIG. 1 is a block diagram illustrating an example imaging systemincluding a pixel array having pixel cells and read out circuitry toimprove the power supply rejection ratio in bit lines in accordance withthe teachings of the present invention.

FIG. 2 is a schematic illustrating one example of read out circuitry ofan image sensing system that improves the power supply rejection ratioin bit lines in accordance with the teachings of the present invention.

FIG. 3 is a schematic illustrating one example in greater detail of aread out circuit of an image sensing system that improves the powersupply rejection ratio in bit lines in accordance with the teachings ofthe present invention.

Corresponding reference characters indicate corresponding componentsthroughout the several views of the drawings. Skilled artisans willappreciate that elements in the figures are illustrated for simplicityand clarity and have not necessarily been drawn to scale. For example,the dimensions of some of the elements in the figures may be exaggeratedrelative to other elements to help to improve understanding of variousembodiments of the present invention. Also, common but well-understoodelements that are useful or necessary in a commercially feasibleembodiment are often not depicted in order to facilitate a lessobstructed view of these various embodiments of the present invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Itwill be apparent, however, to one having ordinary skill in the art thatthe specific detail need not be employed to practice the presentinvention. In other instances, well-known materials or methods have notbeen described in detail in order to avoid obscuring the presentinvention.

Reference throughout this specification to “one embodiment”, “anembodiment”, “one example” or “an example” means that a particularfeature, structure or characteristic described in connection with theembodiment or example is included in at least one embodiment of thepresent invention. Thus, appearances of the phrases “in one embodiment”,“in an embodiment”, “one example” or “an example” in various placesthroughout this specification are not necessarily all referring to thesame embodiment or example. Furthermore, the particular features,structures or characteristics may be combined in any suitablecombinations and/or subcombinations in one or more embodiments orexamples. Particular features, structures or characteristics may beincluded in an integrated circuit, an electronic circuit, acombinational logic circuit, or other suitable components that providethe described functionality. In addition, it is appreciated that thefigures provided herewith are for explanation purposes to personsordinarily skilled in the art and that the drawings are not necessarilydrawn to scale.

Examples in accordance with the teaching of the present inventiondescribe an image sensor read out circuit that includes a current mirrorcircuit having a first current path and a second current path. In oneexample, a first current conducted through the first current path isused to control a second current in the second current path of thecurrent mirror circuit. In one example, the second current path of thecurrent mirror circuit is coupled to an amplifier transistor of a pixelcircuit of the image sensor such that the second current is conductedthrough the amplifier transistor. In the example, a first current sourcecoupled to the first current path of the first current mirror circuit isutilized to provide a substantially constant current component of thefirst current. A second current source coupled to a power supply rail ofthe pixel circuit is also coupled to the first current path of the firstcurrent mirror circuit to provide a ripple current component of thefirst current. In the example, the ripple current component provided bythe second current source is responsive to a ripple in the power supplyrail of the pixel circuit. Thus, in the example the first current issubstantially equal to a sum of the substantially constant currentcomponent provided by the first current source and the ripple currentcomponent provided by the second current source in accordance with theteachings of the present invention. Since the ripple current componentprovided by the second current source is responsive to a ripple in thepower supply rail, which may be caused for example by noise in the powersupply, ripples in the current through the amplifier transistor havesubstantially the same phase and frequency as the noise in the powersupply rail, which therefore provides an improved power supply rejectionratio in accordance with the teachings of the present invention.

To illustrate, FIG. 1 is a schematic illustrating one example of animage sensing system 100 that includes a read out circuit 110 thatprovides an improved power supply rejection ratio in accordance with theteachings of the present invention. As shown in the depicted example,imaging system 100 includes pixel array 105 coupled to control circuitry120 and read out circuit 110, which is coupled to function logic 115.

In one example, pixel array 105 is a two-dimensional (2D) array ofimaging sensors or pixel cells (e.g., pixel cells P1, P2 . . . , Pn). Inone example, each pixel cell is a CMOS imaging pixel. As illustrated,each pixel cell is arranged into a row (e.g., rows R1 to Ry) and acolumn (e.g., column C1 to Cx) to acquire image data of a person, place,object, etc., which can then be used to render a 2D image of the person,place, object, etc.

In one example, after each pixel cell has accumulated its image data orimage charge, the image data is read out by read out circuit 110 throughcolumn bit lines 109 and then transferred to function logic 115. Invarious examples, read out circuit 110 may also include additionalamplification circuitry, additional analog-to-digital (ADC) conversioncircuitry, or otherwise. Function logic 115 may simply store the imagedata or even manipulate the image data by applying post image effects(e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast,or otherwise). In one example, read out circuit 110 may readout a row ofimage data at a time along readout column bit lines 109 (illustrated) ormay read out the image data using a variety of other techniques (notillustrated), such as a serial readout or a full parallel readout of allpixels simultaneously.

In one example, control circuitry 120 is coupled to pixel array 105 tocontrol operational characteristics of pixel array 105. For example,control circuitry 120 may generate a shutter signal for controllingimage acquisition. In one example, the shutter signal is a globalshutter signal for simultaneously enabling all pixels within pixel array105 to simultaneously capture their respective image data during asingle acquisition window. In another example, the shutter signal is arolling shutter signal such that each row, column, or group of pixels issequentially enabled during consecutive acquisition windows.

FIG. 2 is a schematic illustrating one example of a read out circuit 210of an image sensing system that improves the power supply rejectionratio in bit lines in accordance with the teachings of the presentinvention. In one example, it is appreciated that read out circuit 210of FIG. 2 may be one example of read out circuit 110 of FIG. 1, and thatsimilarly named and numbered elements referenced below may be coupledand function similar to as described above. As shown in the exampledepicted in FIG. 2, read out circuit 210 includes a current mirrorcircuit 221 having a first current path 222 and a second current path223. Current mirror circuit 221 includes a transistor 225 and atransistor 227, each having their respective control terminals coupledtogether as shown. In the illustrated example, transistors 225 and 227are MOSFETs with their gate terminals coupled together. As shown in theexample, the gate terminal of transistor 225 is also coupled to thedrain terminal of transistor 225. In the example, the first current path222 is coupled to transistor 225 and the second current path 223 iscoupled to transistor 227 as shown. In the example, a second current 243that is conducted through the second current path 223 is controlled inresponse to a first current 241 that is conducted through the firstcurrent path 222 of current mirror circuit 221.

In the example depicted in FIG. 2, a portion of an example pixel circuit205 is illustrated, which in one example may be a portion of one of theexample pixel cells P1, P2 . . . , Pn of pixel array 105 of FIG. 1. Asshown in the example of FIG. 2, pixel circuit 205 includes an amplifiertransistor 229 coupled to a power supply rail 233, and a floatingdiffusion node FD. In the illustrated example, amplifier transistor 229is a MOSFET that is coupled as a source follower to amplify a signalthat is on the floating diffusion node FD of pixel circuit 205. Thefloating diffusion node FD is coupled to the gate terminal of transistor229 as shown to output the image data as output signal 231 of pixelcircuit 205 from the source terminal of transistor 229 to the bit lines,such as for example bit lines 109 of FIG. 1. As shown in the exampledepicted in FIG. 2, the drain terminal of transistor 229 is coupled toreceive AVDD from power supply rail 233.

As shown in the example depicted in FIG. 2, the second current path 223of the current mirror circuit 221 is coupled to amplifier transistor 229of a pixel circuit 205 through a transistor 245. Accordingly, the outputcurrent I_(OUT) that is conducted through amplifier transistor 229 isalso the second current 243 that is conducted through the second currentpath 223, which is controlled in response to a first current 241 that isconducted through the first current path 222 of current mirror circuit221 in accordance with the teachings of the present invention.

In the example depicted in FIG. 2, the first current path 222 is coupledto receive a first current I_(BG) 247 from a first current source 237,and a second current I_(ΔAVDD) 249 from a second current source 239 suchthat the first current 241 that is conducted through the first currentpath 222 of current mirror circuit 221 is substantially equal to the sumof first current I_(BG) 247 and second current I_(ΔAVDD) 249. In oneexample, first current source 237 is an adjustable ideal bandgap biascurrent source that provides a substantially constant current componentof the first current 241 that does not change with the noise and ripplein the AVDD power supply rail 233. In the example, first current source237 provides the substantially constant current once the trimming hasbeen completed. In the example, second current source 239 is anadjustable bias current source that is coupled to power supply rail 233to provide a ripple current component of the first current 241 that isresponsive to ripple ΔAVDD that occurs in the power supply rail 233. Inthe example, second current source 239 is an adjustable bias currentsource that changes with the AVDD power supply rail 233 in the samephase and frequency.

As mentioned, both first current source 237 and second current source239 are adjustable in the depicted example. In one example, by adjustingthe ratio of the two current sources, the second current 243 throughamplifier transistor 229 can be controlled to satisfy a number ofconditions. One condition is a direct current (DC) condition in whichthe average current 243 through the amplifier transistor 229 can be setto be substantially equal to a design value of the amplifier transistor229, such as for example several μA. A second condition is analternating current (AC) condition in which the current 243 through theamplifier transistor 229 can be set to produce a ΔVDS voltage dropripple across the amplifier transistor 229 that is responsive to thephase and frequency of the ΔAVDD voltage ripple in the power supply rail233. As such, a feed-forward technique of utilizing the ΔAVDD voltageripple in the power supply rail 233 as shown is utilized to produce acorresponding ΔVDS voltage drop ripple across the amplifier transistor229, which compensates for the ripple and noise in the power supply, andtherefore improves the power supply rejection ratio in accordance withthe teachings of the present invention.

FIG. 3 is a schematic illustrating one example in greater detail of aread out circuit 310 of an image sensing system that improves the powersupply rejection ratio in bit lines in accordance with the teachings ofthe present invention. In one example, it is appreciated that read outcircuit 310 of FIG. 3 may be one example of read out circuit 110 of FIG.1 or one example of read out circuit 210 of FIG. 2, and that similarlynamed and numbered elements referenced below may be coupled and functionsimilar to as described above. As shown in the example depicted in FIG.3, read out circuit 310 includes a first current mirror circuit 321having a first current path 322 and a second current path 323. The firstcurrent mirror circuit 321 includes a transistor 325 and a transistor327 having their control terminals coupled together as shown. In theillustrated example, transistors 325 and 327 are MOSFETs with their gateterminals coupled together. As shown in the example, the gate terminalof transistor 325 is also coupled to the drain terminal of transistor325. In the example, the first current path 322 is conducted throughtransistor 325 and the second current path 323 is conducted throughtransistor 327 as shown. In the example, a second current 343 that isconducted through the second current path 323 is controlled in responseto a first current 341 that is conducted through the first current path322 of the current mirror circuit 321.

In the example depicted in FIG. 3, a portion of an example pixel circuit305 is illustrated, which in one example may be a portion of one of theexample pixel cells P1, P2 . . . , Pn of pixel array 105 of FIG. 1, orone example of pixel circuit 205 of FIG. 2. Accordingly, similarly namedand numbered elements referenced below may be coupled and functionsimilar to as described above. As shown in the example of FIG. 3, pixelcircuit 305 includes an amplifier transistor 329 coupled to a powersupply rail 333, and a floating diffusion node FD. In the illustratedexample, amplifier transistor 329 is a MOSFET that is coupled as asource follower to amplify the signal that is on the floating diffusionnode FD, which is coupled to the gate terminal of transistor 329 asshown to output the image data as output signal 331 of pixel circuit 305from the source terminal of transistor 329 to the bit lines, such as forexample bit lines 109 of FIG. 1. As shown in the example depicted inFIG. 3, the drain terminal of transistor 329 is coupled to receive AVDDfrom power supply rail 333.

As shown in the example depicted in FIG. 3, the second current path 323of the current mirror circuit 321 is coupled to amplifier transistor 329of a pixel circuit 305 through a transistor 345. Accordingly, the outputcurrent I_(OUT) that is conducted through amplifier transistor 329 isalso the second current 343 that is conducted through the second currentpath 323, which is controlled in response to a first current 341 that isconducted through the first current path 322 of current mirror circuit321 in accordance with the teachings of the present invention.

In the example depicted in FIG. 3, the first current path 322 is coupledto receive a first current I_(BG) 347 from a first current source 337,and a second current I_(ΔAVDD) 349 from a second current source 339 suchthat the first current 341 that is conducted through the first currentpath 322 of current mirror circuit 321 is substantially equal to the sumof first current I_(BG) 347 and second current I_(ΔAVDD) 349.

In one example, first current source 337 is an adjustable ideal bandgapbias current source that provides a substantially constant currentI_(BG) component of the first current 341 that does not change with theΔAVDD ripple of power supply rail 333. In the example, first currentsource 337 provides the substantially constant current once the currentadjustment has been completed. In the example, second current source 339is an adjustable bias current source that is coupled to power supplyrail 333 to provide a ripple current component of the first current 341that is responsive to ΔAVDD ripple that occurs in the power supply rail333. In the example, second current source 339 is an adjustable biascurrent source that changes at the same phase and frequency with theΔAVDD ripple that occurs in power supply rail 333.

As shown in the example depicted in FIG. 3, first current source 337includes a bandgap reference current source 351, which is an idealbandgap bias current source that provides a substantially constantcurrent that does not change with the ΔAVDD ripple of power supply rail333. In the example, first current source 337 also includes a secondcurrent mirror circuit 353 having a first current path 355 coupled tothe bandgap reference current source 351. In one example, second currentmirror circuit 353 also includes a second current path 357 coupled tothe first current path 322 of the first current mirror circuit 321. Asshown in the depicted example, second current path 357 is one of aplurality of switched current paths, including second current path 357and a third current path 359, which are coupled to the first currentpath 322 of first current mirror circuit 321. In the illustratedexample, second current path 357 is switched using transistor 367 inresponse to a trim signal TRIM_(A1), and third current path 359 isswitched using transistor 369 in response to a trim signal TRIM_(AN). Inthe example, the trim signals TRIM_(A1) . . . TRIM_(AN) may be used toadjust the substantially constant current I_(BG) 347 in accordance withthe teachings of the present invention.

In the depicted example, the second current mirror circuit 353 alsoincludes a plurality of transistors, including transistor 375,transistor 377, and transistor 379, each having their respective controlterminals coupled together as shown. In the illustrated example,transistors 375, 377, and 329 are MOSFETs with their gate terminalscoupled together. As shown in the example, the gate terminal oftransistor 375 is also coupled to the drain terminal of transistor 375.In the example, the first current path 355 of second current mirrorcircuit 353 is conducted through transistor 375, the second current path357 of second current mirror circuit 353 is conducted through transistor377, and the third current path 359 is conducted through transistor 379as shown. In the example, the currents that are conducted through thesecond current path 357 and third current path 359 are controlled inresponse to the current through the first current path 355 of the secondcurrent mirror circuit 353.

In the example depicted in FIG. 3, second current source 339 includes aplurality of switched current paths, including current path 361 andcurrent path 363, which are coupled to the first current path 322 offirst current mirror circuit 321 to provide the ripple current componentof the first current 341 that is responsive to ripple ΔAVDD that occursin the power supply rail 333 in accordance with the teachings of thepresent invention. In the illustrated example, current path 361 isswitched using transistor 371 in response to a trim signal TRIM_(B1),and current path 363 is switched using transistor 373 in response to atrim signal TRIM_(BN). In the example, the trim signals TRIM_(B1) . . .TRIM_(BN) may be used to adjust the ripple current component I_(ΔAVDD)349 in accordance with the teachings of the present invention.

In the depicted example, second current source 339 also includes aplurality of transistors, including transistor 381 and transistor 383each having their respective control terminals coupled to the powersupply rail 333 as shown. In the illustrated example, transistors 381and 383 are self-biased MOSFETs with their gate terminals coupled totheir source terminals as well as to power supply rail 333 as shown.With their respective gate terminals coupled as shown in FIG. 3, therespective currents conducted through transistors 381 and 383 areresponsive to the power supply rail 333 and therefore have the samephase and frequency of the ΔAVDD ripple that occurs in the power supplyrail 333 in accordance with the teachings of the present invention. Withthe switched current paths provided with transistors 371 and 373discussed above, the currents provided by transistors 381 and 383provided digital bias sources that are digitally adjustable.

By utilizing the trim signals TRIM_(A1) . . . TRIM_(AN) to adjust thefirst current source 337, and utilizing the trim signals TRIM_(B1) . . .TRIM_(BN) to adjust the second current source 339, an optimized ratiobetween the first current source 337 and second source 339 can obtainedto provide an optimized ratio of the two current sources 337 and 339 tomeet DC and AC conditions discussed above at the same time in accordancewith the teachings of the present invention.

In one example, read out circuit 310 also includes an adjustablecapacitor C1 365 coupled between power supply rail 333 and the controlterminal of transistor 327. Thus, as shown in the example depicted inFIG. 3, the gate terminal of transistor 327 is capacitively coupled, orAC coupled, to power supply rail 333 through adjustable capacitor C1365. In one example, a capacitor C2 385 is also coupled between the gateterminal of transistor 327 and ground. With the capacitive or ACcoupling of the gate terminal of transistor 327 to the power supply rail333, when there is ΔAVDD ripple in the power supply rail 333, the ripplewill be capacitively coupled to the gate terminal of transistor 327. Asa result, the ΔAVDD ripple in the power supply rail 333 affects thesecond current 343 that is conducted through the second current path 323through the amplifier transistor 329 in accordance with the teachings ofthe present invention. In other words, if it is assumed that transistor327 is an output transistor and that the second current 343 conductedthrough transistor 327 and amplifier transistor 329 is an output currentthat is conducted through output current path 323, the effect of theΔAVDD ripple in the power supply rail 333 on the second current 343results in a corresponding ΔVDS voltage across the amplifier transistor329 with the same phase and frequency. The corresponding ΔVDS voltageacross the amplifier transistor 329 in response to the ripple in thepower supply rail 333 compensates for the ripple that in power supplyrail 333, which improves the power supply rejection ratio in accordancewith the teachings of the present invention.

In an alternate example, it is appreciated that with adjustablecapacitor C1 365 coupled between power supply rail 333 and the controlgate transistor 327, the first current source 337 and second currentsource 339 are optional in read out circuit 310 and that the ΔAVDDripples in the power supply rail 333 may be compensated with adjustablecapacitor C1 365 to improve the power supply rejection ratio inaccordance with the teachings of the present invention.

In one example, the capacitance of adjustable capacitor C1 365 may betrimmed in response to a trim signal TRIM_(C) to tune the amount ofcapacitance and compensation to be provided by adjustable capacitor C1365. In one example, adjustable capacitor C1 365 may be implementedusing a variety of techniques, including for example a single adjustablemetal-to-metal capacitor, or any other adjustable capacitance technique,such as for example utilizing switched metal 1 and metal 2 layers in anintegrated circuit chip in accordance with the teachings of the presentinvention.

The above description of illustrated examples of the present invention,including what is described in the Abstract, are not intended to beexhaustive or to be limitation to the precise forms disclosed. Whilespecific embodiments of, and examples for, the invention are describedherein for illustrative purposes, various equivalent modifications arepossible without departing from the broader spirit and scope of thepresent invention.

These modifications can be made to examples of the invention in light ofthe above detailed description. The terms used in the following claimsshould not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims. Rather, thescope is to be determined entirely by the following claims, which are tobe construed in accordance with established doctrines of claiminterpretation. The present specification and figures are accordingly tobe regarded as illustrative rather than restrictive.

What is claimed is:
 1. An image sensor read out circuit, comprising: afirst current mirror circuit having a first current path and a secondcurrent path, wherein a second current conducted through the secondcurrent path of the first current mirror circuit is controlled inresponse to a first current conducted through the first current path ofthe first current mirror circuit, wherein the second current path of thefirst current mirror circuit is coupled to an amplifier transistor of apixel circuit of an image sensor, wherein the second current isconducted through the amplifier transistor; a first current sourcecoupled to the first current path of the first current mirror circuit toprovide a substantially constant current component of the first current;and a second current source coupled to a power supply rail of the pixelcircuit and coupled to the first current path of the first currentmirror circuit to provide a ripple current component of the firstcurrent, wherein the ripple current component provided by the secondcurrent source is responsive to a ripple in the power supply rail,wherein the first current is responsive to a sum of the substantiallyconstant current component provided by the first current source and theripple current component provided by the second current source.
 2. Theimage sensor read out circuit of claim 1 wherein the first currentsource comprises a bandgap reference circuit coupled to provide asubstantially constant reference substantially independent of the rippleof the power supply rail.
 3. The image sensor read out circuit of claim1 wherein the first current source is adjustable.
 4. The image sensorread out circuit of claim 3 wherein the first current source comprises afirst plurality of switched current paths coupled to the first currentpath of the first current mirror circuit to adjust the substantiallyconstant current component provided by the first current source.
 5. Theimage sensor read out circuit of claim 1 wherein the first currentsource comprises a second current mirror circuit including at least afirst current path and a second current path, wherein the first currentpath of the second current mirror circuit is coupled to a bandgapreference circuit, and wherein the second current path of the secondcurrent mirror circuit is coupled to the first current path of the firstcurrent mirror circuit.
 6. The image sensor read out circuit of claim 1wherein the second current source is adjustable.
 7. The image sensorread out circuit of claim 6 wherein the second current source comprisesa second plurality of switched current paths coupled to the firstcurrent path of the first current mirror circuit to adjust the ripplecurrent component provided by the second current source.
 8. The imagesensor read out circuit of claim 1 wherein a control terminal of anoutput transistor included in the second current path of the firstcurrent mirror is capacitively coupled to the power supply rail.
 9. Theimage sensor read out circuit of claim 1 further comprising anadjustable capacitance coupled between the power supply rail and acontrol terminal of an output transistor included in the second currentpath of the first current mirror.
 10. An imaging system comprising: apixel array including a plurality of pixel circuits, wherein each one ofthe pixel circuits includes an amplifier transistor coupled to generatean output signal of the pixel circuit; control circuitry coupled to thepixel array to control operation of the pixel array; and read outcircuitry coupled to the pixel array to read out image data from thepixel array, wherein the read out circuitry includes: a first currentmirror circuit having a first current path and a second current path,wherein a second current conducted through the second current path ofthe first current mirror circuit is controlled in response to a firstcurrent conducted through the first current path of the first currentmirror circuit, wherein the second current path of the first currentmirror circuit is coupled to the amplifier transistor of a pixel circuitof an image sensor, wherein the second current is conducted through theamplifier transistor; a first current source coupled to the firstcurrent path of the first current mirror circuit to provide asubstantially constant current component of the first current; and asecond current source coupled to a power supply rail of the pixelcircuit and coupled to the first current path of the first currentmirror circuit to provide a ripple current component of the firstcurrent, wherein the ripple current component provided by the secondcurrent source is responsive to a ripple in the power supply rail,wherein the first current is responsive to a sum of the substantiallyconstant current component provided by the first current source and theripple current component provided by the second current source.
 11. Theimaging system of claim 10 further comprising function logic coupled tothe read out circuitry to store the image data read out from the pixelarray.
 12. The imaging system of claim 10 wherein the first currentsource comprises a bandgap reference circuit coupled to provide asubstantially constant reference substantially independent of the rippleof the power supply rail.
 13. The imaging system of claim 10 wherein thefirst current source is adjustable.
 14. The imaging system of claim 13wherein the first current source comprises a first plurality of switchedcurrent paths coupled to the first current path of the first currentmirror circuit to adjust the substantially constant current componentprovided by the first current source.
 15. The imaging system of claim 10wherein the first current source comprises a second current mirrorcircuit including at least a first current path and a second currentpath, wherein the first current path of the second current mirrorcircuit is coupled to a bandgap reference circuit, and wherein thesecond current path of the second current mirror circuit is coupled tothe first current path of the first current mirror circuit.
 16. Theimaging system of claim 10 wherein the second current source isadjustable.
 17. The imaging system of claim 16 wherein the secondcurrent source comprises a second plurality of switched current pathscoupled to the first current path of the first current mirror circuit toadjust the ripple current component provided by the second currentsource.
 18. The imaging system of claim 10 wherein a control terminal ofan output transistor included in the second current path of the firstcurrent mirror is capacitively coupled to the power supply rail.
 19. Theimaging system of claim 10 further comprising an adjustable capacitancecoupled between the power supply rail and a control terminal of anoutput transistor included in the second current path of the firstcurrent mirror.
 20. An image sensor read out circuit, comprising: anoutput transistor coupled to an output current path coupled to anamplifier transistor of a pixel circuit of the image sensor, wherein anoutput current through the output current path is conducted through theamplifier transistor; and an adjustable capacitance coupled between apower supply rail and a control terminal of the output transistor suchthat a ripple in the power supply rail is capacitively coupled throughthe adjustable capacitance to the control terminal of the outputtransistor to affect the output current through the amplifier transistorin response to the ripple in the power supply rail.
 21. The image sensorread out circuit of claim 20 wherein the amplifier transistor of a pixelcircuit of the image sensor is coupled to the power supply rail.
 22. Theimage sensor read out circuit of claim 20 further comprising a firstcurrent mirror circuit having a first current path and a second currentpath, wherein a second current conducted through the second current pathof the first current mirror circuit is controlled in response to a firstcurrent conducted through the first current path of the first currentmirror circuit, wherein the second current path is the output currentpath.
 23. The image sensor read out circuit of claim 22 furthercomprising a first current source coupled to the first current path ofthe first current mirror circuit to provide a substantially constantcurrent component of the first current.
 24. The image sensor read outcircuit of claim 23 further comprising a second current source coupledto the power supply rail of the pixel circuit and coupled to the firstcurrent path of the first current mirror circuit to provide a ripplecurrent component of the first current, wherein the ripple currentcomponent provided by the second current source is responsive to theripple in the power supply rail, wherein the first current is equal to asum of the substantially constant current component provided by thefirst current source and the ripple current component provided by thesecond current source.